1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection device in an integrated circuit (IC). In particular, the present invention relates to an input/output (I/O) cell capable of uniform ESD current discharge during an ESD event.
2. Description of the Related Art
ESD in electronic devices has been a major obstacle to product reliability. Electrostatic charge can accumulate in a human body, a machine or an electric device of up to several thousand volts. Contact with another, typically a grounded object, causes electrostatic discharge, which travels through a path and may damage any device along the path if the device is not well protected.
There are several known test models, such as Human Body Mode (HBM), Machine Mode (MM), and others, to simulate different conditions under which ESD occurs. An electronic device can only be certified for commercialized after passing tests of a certain level for each test model.
Each advanced IC has millions of devices in a tiny chip and, as such, is highly vulnerable to ESD stress. In order to prevent ESD damage and achieve commercial certification, each IC must be well designed and protected. FIG. 1 shows an IC. In the IC 10, core circuit 12 directs internal operation while I/O cells 14 are responsible for communication between core circuit 12 and other external ICs through pads 16 and pins (not shown). Circuit designers are primarily concerned with setting up a discharge path which is capable of both sustaining heat dissipation generated by ESD and maintaining workable thereafter. It is known that electrostatic charge generally occurs outside an IC. If it can be discharged near pads 16, where electrostatic charge first enters IC 10, it will not reach and damage core circuit 12, which is typically weaker than the I/O cells. Hence I/O cells 14 are always a topic of discussion in the art of ESD protection.
One way to provide ESD protection in an I/O cell is to utilize metal-on-semiconductor transistors (MOSs) in the post driver of an I/O cell. Referring to FIG. 2, an exemplary I/O cell with a post driver 20 and a pre-driver 18 is presented. Pre-driver 18 directs-simple logical or analog functions of the I/O cell, such as tri-state, level shift, and others. In addition to signal transferring for pre-driver 18, post driver 20 is responsible for driving a pad and a pin in an IC, the wire between the IC and another connected IC, and a pad and a pin in the connected IC, essentially forming a huge parasitic capacitor. Therefore, in a post driver capable of driving the huge parasitic capacitor, the negative-type MOS (NMOS) and the positive-type MOS (PMOS) requires a large layout area. To reduce occupied space in a silicon area, a MOS with large driving ability is typically laid out as a finger-type MOS, comprising several gate fingers 22, source regions 24 and drain regions 26. FIG. 3 illustrates an exemplary layout of a finger-type NMOS in a post driver. Each gate finger 22 is located between one of the source regions 24 and one of the drain regions 26. Regarding the ESD issue, the amount of area allocated is critical, as it must be large enough to dissipate the heat generated by ESD current to prevent burnout thereof. Due to the large area occupied by the NMOS and PMOS, the post driver is considered a suitable candidate for use as an ESD protection device. For example, in FIG. 2, while a positive ESD pulse occurs at pad 16 and VSS is grounded, the NPN BJT (bipolar junction transistor) parasitic under the NMOS “snaps back” to a low impedance condition and conducts ESD current to release ESD stress generated thereby.
Another approach is to employ a silicon controlled rectifier (SCR). SCR is famous for its low impedance and low holding voltage while “turned on”. Therefore, SCR generates far less heat while turned on to conduct ESD current during an ESD event. Put simply, to achieve a certain ESD robustness or protection level, SCR requires less silicon area than other devices, offering a reduced cost. FIG. 4 shows a simple SCR connected between pad1 30 and pad2 32. The path for ESD current IESD is also indicated in FIG. 4. FIG. 5 shows a modified version of SCR, which includes a NMOS 40 with a source/drain region 38 located on the junction between P-substrate 34 and N-well 36 to lower the trigger voltage of the SCR. Other ESD protection devices that at least combine a SCR with a MOS are also taught in US patents, such as U.S. Pat. No. 5,742,085 and U.S. Pat. No. 6,147,369.